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 TECHNICAL DATA
KK74HC05A Hex Inverter with Open-Drain Outputs
The KK74HC05A is identical in pinout to the LS/ALS05. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALS TTL outputs. This device contains six independent gates, each of which performs the logic INVERT function. The open-drain outputs require external pullup resistors for proper logical operation. They may be connected to other open-drain outputs to implement active-high wired-AND functions. * * * * Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1.0 A High Noise Immunity Characteristic of CMOS Devices ORDERING INFORMATION KK74HC05AN Plastic KK74HC05AD SOIC TA = -55 to 125 C for all packages
LOGIC DIAGRAM
PIN ASSIGNMENT
FUNCTION TABLE
Inputs A L H Output Y Z L
Z = High Impedance PIN 14 =VCC PIN 7 = GND
1
KK74HC05A
MAXIMUM RATINGS*
Symbol VCC VIN VOUT IIN IOUT ICC PD Tstg TL
*
Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP SOIC Package** Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package)
**
Value -0.5 to +7.0 -1.5 to VCC +1.5 -0.5 to VCC +0.5 20 25 50 750 500 -65 to +150 260
Unit V V V mA mA mA mW C C
Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. ** Derating - Plastic DIP: - 10 mW/C from 65 to 125C SOIC Package: - 7 mW/C from 65 to 125C
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VIN, VOUT TA tr, tf Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) VCC =2.0 V VCC =4.5 V VCC =6.0 V Min 2.0 0 -55 0 0 0 Max 6.0 VCC +125 1000 500 400 Unit V V C ns
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
2
KK74HC05A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Symbol Parameter Test Conditions VCC V Guaranteed Limit 25 C to -55C 0.5 1.35 1.8 85 C 0.5 1.35 1.8 125 C 0.5 1.35 1.8 V Unit
VIL
Low -Level Input Voltage
VOUT= VCC or 0 V IOUT 0.5 A (= -55 to 25C) IOUT 5.0 A (= 85C) IOUT 10 A (= 125C) VOUT 0.1 V IOUT 20 A VIN=VIH IOUT 20 A VIN=VIH IOUT 4.0 mA VIN=VIH IOUT 5.2 mA
2.0 4.5 6.0
VIH
High-Level Input Voltage Low - Level Output Voltage
2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 6.0 6.0 6.0
1.5 3.15 4.2 0.1 0.1 0.1 0.26 0.26 -0.1 -0.1 1.0
1.5 3.15 4.2 0.1 0.1 0.1 0.33 0.33 -1.0 -1.0 10
1.5 3.15 4.2 0.1 0.1 0.1 0.4 0.40 -1.0 -1.0 40
V
VOL
V
IIL IIH ICC
Input Leakage Current Input Leakage Current Quiescent Supply Current (per Package) Three-State Leakage Current Three-State Leakage Current
VIL= GND VIH=VCC VIL=GND VIH=VCC IOUT=0 A VIN= VIL or VIH VOUT= GND VIN= VIL or VIH VOUT= VCC
A A A
IOZL IOZH
6.0 6.0
-0.5 -0.5
-5.0 -5.0
-10 -10
A A
3
KK74HC05A
AC ELECTRICAL CHARACTERISTICS (CL=50pF,Input tr=tf=6.0 ns)
Symbol Parameter Test Conditions VCC V Guaranteed Limit 25 C to -55C 120 24 20 85 C 150 30 26 125 C 180 36 31 ns Unit
tPLZ, tPZL
Propagation Delay, Input A to Output Y (Figures 1 and 2)
VIL = GND VIH = VCC tLH = tHL = 6 ns CL = 50 pF
2.0 4.5 6.0
tTHL
Output Transition Time, Any Output (Figures 1 and 2) Input Capacitance Three-State Output Capacitance (Output in HighImpedance State)
VIL = GND VIH = VCC tLH = tHL = 6 ns CL = 50 pF
2.0 4.5 6.0
75 15 13 10 10
95 19 16 10 10
110 22 19 10 10
ns
CIN COUT
pF pF
Power Dissipation Capacitance (Per Gate) CPD Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC
Typical @25C,VCC=5.0 V 8.0 pF
4
KK74HC05A
tr
90% 50% 10%
tf VCC GND tPLZ HIGH IMPEDANCE VOL
INPUT OUTPUT Y
tPZL
90% 50% 10%
10%
tPHL
Figure 1. Switching Waveforms
VCC
RPD OUTPUT DEVICE UNDER TEST TEST POINT CL*
* Includes all probe and jig capacitance
Figure 2. Test Circuit
VCC OUTPUT PROTECTION DIODE Y A
Figure 3. Expanded Logic Diagram (1/6 of the Device)
5
KK74HC05A
N SUFFIX PLASTIC DIP (MS - 001AA)
A 14 8 B 1 7
Dimension, mm Symbol A B C MIN 18.67 6.1 MAX 19.69 7.11 5.33 0.36 1.14 2.54 7.62 0 2.92 7.62 0.2 0.38 10 3.81 8.26 0.36 0.56 1.78
F
L
D F
C -T- SEATING N G D 0.25 (0.010) M T K
PLANE
G H
H J
M
J K L M N
NOTES: 1. Dimensions "A", "B" do not include mold flash or protrusions. Maximum mold flash or protrusions 0.25 mm (0.010) per side.
D SUFFIX SOIC (MS - 012AB) Dimension, mm
8
A 14
Symbol A
MIN 8.55 3.8 1.35 0.33 0.4 1.27 5.27 0 0.1 0.19 5.8 0.25
MAX 8.75 4 1.75 0.51 1.27
H
B
P
B C
1
G
7 C R x 45
D F G
-TD 0.25 (0.010) M T C M K
SEATING PLANE
H
J F M
J K M P R
8 0.25 0.25 6.2 0.5
NOTES: 1. Dimensions A and B do not include mold flash or protrusion. 2. Maximum mold flash or protrusion 0.15 mm (0.006) per side for A; for B 0.25 mm (0.010) per side.
6


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